Dual-level or multi-level metalization schemes for integrated circuits are well known and have numerous advantages including smaller integrated circuit die size, increased device speed, ease of design, as well as advantages related to the planarization of device topology.
One of the disadvantages of a multi-level metalization is the increased number of processing steps due to the deposition, patterning, and etching of the required additional metal, oxide, and passivation layers. While the additional processing steps are generally compatible with standard silicon-based integrated circuits, the additional processing steps may adversely affect ferroelectric integrated circuit devices. For example, hydrogen generated during any of the subsequent processing steps may adversely affect the integrity of the ferroelectric dielectric layer of a ferroelectric capacitor, resulting in degraded electrical performance.
What is desired, therefore, is a dual-level metalization method and structure that is compatible with a ferroelectric-based integrated circuit.